The introduction of the VPlan model in Loop Vectorizer (LV) started as a refactoring effort to overcome LV’s existing limitations and extend its vectorization capabilities to outer loops. So far, progress has been made on the refactoring part by introducing the VPlan model to record the vectorization and unrolling decisions for candidate loops and generate code out of them. This talk focuses on the strategy to bring outer loop vectorization capabilities to Loop Vectorizer by introducing an alternative vectorization path in LV that builds VPlan upfront in the Loop Vectorizer pipeline. We discuss how this approach, in the short term, will add support for vectorizing a subset of simple outer loops annotated with vectorization directives (#pragma omp simd and #pragma clang loop vectorize). We also talk about the plan to extend the support towards generic outer and inner loop auto-vectorization through the convergence of both vectorization paths, the new alternative vectorization path and the existing inner loop vectorizer path, into a single one with advanced VPlan-based vectorization capabilities.
We conclude the talk by describing potential opportunities for the LLVM community to collaborate in the development of this effort.
Joint work of the Intel’s vectorizer team.
[1] RFC: Proposal for Outer Loop Vectorization Implementation Plan, December 2017, http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html [2] Extending LoopVectorizer towards supporting OpenMP4.5 SIMD and outer loop auto-vectorization, 2016 LLVM Developers' Meeting, https://www.youtube.com/watch?v=XXAvdUwO7kQ [3] Introducing VPlan to the Loop Vectorizer, 2017 European LLVM Developer’s Meeting, https://www.youtube.com/watch?v=IqzJRs6tb7Y [4] Vectorizing Loops with VPlan – Current State and Next Steps, 2017 LLVM Developer’s Meeting, https://www.youtube.com/watch?v=BjBSJFzYDVk
